The Chips JU EdgeAI project was present at the European Nanoelectronics Applications, Design & Technology Conference – ADTC 2025, May 14-16, 2025, Grenoble, France, and represented by STMicroelectronics, SINTEF and INPG – University of Grenoble Alpes.
The European Nanoelectronics Applications, Design and Technology Conference focuses on electronic components, electronic system design, design automation, and manufacturing topics related to micro- and nanoelectronics, which are critical to success for many European companies. EUREKA, Horizon Europe, and local governments have supported exhaustive research and development in this area in recent years. This conference will highlight the exciting and promising results primarily from the PENTA/XECS, ECSEL/KDT/Chips JU & H2020/HE and IPCEI ME/CT projects.
This annual event clearly focused on deep technical discussions between the leading European experts in the addressed fields, independent from the research programs where the individual projects were started. European projects on electronic system design, design technology, and manufacturing topics have been invited to contribute to the conference.
Ovidiu Vermesan, SINTEF, Ana Pinzari. INPG – University of Grenoble Alpes, Antonio-Marcello Coppola, STMicroelectronics at ADTC 2025 Grenoble France.
Antonio-Marcello Coppola, STMicroelectronics, co-chaired the conference with Gilles Sicard, CEA Leti, France, and highlighted the importance of developing edge AI in nanoelectronics technologies and applications.
Ovidiu Vermesan, SINTEF, co-chaired Technical Session 4: Spintronic and Quantum Sensing and Communication together with Patrick Cogez, AENEAS, France, and actively participated in the discussions on the topics addressed by the different sessions, such as neuromorphic computing, CAD tools based on AI, software-defined vehicles (SDVs), chiplets, and sustainability.
Ana Pinzari, INPG – University of Grenoble Alpes, presented the work in the Chips JU EdgeAI project, value chain on Agrifood and Beverage and showed the results obtained in the value chain demonstrators addressing the Vineyard – Yield Prediction and Vineyard Disease Identification. The implementation presented the optimisation of object detection edge AI models (YOLOv2-tiny, YOLOv8-custom, RT-DETR), the models’ performance and the validation results using the STM32MP257F-EV1 evaluation board.
The evaluation board is based on the STM32 MP2 developed in the Chips JU EdgeAI project and offering edge AI capabilities, the flexibility to run AI applications on either the CPU, GPU, or NPU, supporting edge computing use cases, such as machine vision, through its multimedia capabilities. The STM32MP2 SoC microprocessor is based on dual-core Arm® Cortex®-A35 64-bit RISC cores, a Cortex®-M33 32-bit RISC core featuring a floating-point unit (FPU) for single-precision data-processing, DSP instructions, a Cortex®-M0+ 32-bit RISC core to ensure very-low-power peripheral activity when other processors and domains are inactive and a 3D graphics processing unit (GPU) including a neural processor unit (NPU) supporting TensorFlow Lite, ONNX, and Linux NN.
Demonstration board using the STM32MP257F-EV1for object identification.