Abstract:
TinyHLS is a Python-based hardware compiler that automatically generates hardware accelerators in the form of HDL-Code for CNNs. The description of the CNN architecture as well as the training is done in advance using Python Keras. TinyHLS reduces the development effort for edge AI applications regarding cost and time. Furthermore, tinyHLS offers a platform independent alternative to commercial high-level synthesis tools like AMD Vivado HLS™. The hardware accelerators generated by tinyHLS are able to perform the inference calculation in digital hardware and allow efficient inference of CNN applications on edge devices. Runtime, as well as energy consumption is reduced by over 95% compared to pure software-based implementations. In this work, the concept of this hardware compiler is presented. The function is demonstrated by implementing an image classification CNN for fruit detection on an FPGA board using tinyHLS. The results in terms of accuracy, latency and area are then discussed based on the implementation of the use-case CNN. Finally, a brief outlook on the improvement of tinyHLS is given, in order to meet requirements of edge AI computing in the future.

Author(s)/Presenter(s): Raphael Gaede, Fraunhofer IMS, Germany.
Ingo Hoyer (1) Fraunhofer IMS, Germany.
Holger Kappert (1) Fraunhofer IMS, Germany.
Filippo Milazzo (2) AGRICOLUS, Italy.
Carsten Rolfes (1) Fraunhofer IMS, Germany.
Karsten Seidl (1,3) Fraunhofer IMS and University of Duisburg-Essen, Germany.

The presenter Raphael Gaede received his B. Eng. degree in mechanical engineering from the University of Applied Sciences Offenburg, Germany, in 2022 and his M.Sc. degree in Biomedical Information Technology from the University of Applied Sciences Dortmund, Germany, in 2025. In the course of his Master Thesis, he developed a hardware compiler for 1D CNNs at Fraunhofer Institute for Microelectronic Circuits and Systems IMS. Since May 2025 he works as a research associate at Fraunhofer IMS and continues his work on hardware compilers for 1D and 2D CNNs. His special research interest is in the field of hardware accelerators for AI. That includes the development and validation of the hardware accelerators as well as their implementation on FPGA boards for demonstration purposes.

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Foundation models based on transformer networks offer exceptional performance and adaptability, making them ideal for numerous application areas. Nevertheless, deploying these models presents unique challenges, especially in today’s efficiency-driven context. Ensuring that these models can perform inference efficiently on mobile devices is vital for their widespread use, all while controlling energy consumption. The primary challenge lies in striking a balance between application efficiency and the compression rate of the data being handled.
In this work, we propose a co-design methodology/framework for the exploration and evaluation of fine-grained Post-Training Quantization strategies with hardware optimization considerations. In particular, it enables to specify quantization policies (methods, weights/activations data-granularity and bit width…) per layer while jointly modelling different hardware implementations. Within this framework, we evaluated a quantization scheme of a Dinov2 foundation model based on a combination of state-of-the-art algorithm that are HW-friendly.

Author(s)/Presenter(s): Erwan Piriou, CEA-List, Université Paris-Saclay, France.
Maria Lepecq, CEA-List, Université Paris-Saclay, France.
Lucas Grativol-Ribeiro, CEA-List, Université Paris-Saclay, France.

The presenter Lucas Grativol-Ribeiro graduated from a PhD in Digital and Engineering Science from IMT Atlantique in 2024. He joined the CEA List as post-doctoral fellow to develop efficient AI hardware mechanisms optimised for sparsity and enhance the interaction between hardware and algorithms for higher energy efficiency and performance.

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Large Language Models (LLMs) are increasingly a key component within Artificial Intelligence (AI) applications for a number of domains. At the same time, executing LLM models on edge devices may allow secure computation and lower energy consumption and cost, but to become practical, performance must improve dramatically. This is due to the significant demands introduced by emerging LLMs in terms of both memory and compute and the reduced availability of them in constrained edge devices. In this talk I will introduce the Glasgow Intelligent Computing Laboratory (gicLAB) and give an overview of our current research on SECDA-LLM, an Hardware-Software co-design platform for developing and deploying efficient AI accelerators for edge LLM inference.

Author(s)/Presenter(s): José Cano, University of Glasgow, Scotland, United Kingdom.
Jude Haris, University of Glasgow, Scotland, United Kingdom.

The presenter José Cano is a Reader (Associate Professor) in the School of Computing Science at the University of Glasgow, where he leads the Glasgow Intelligent Computing Lab (gicLAB) and he is deputy Head of the GLAsgow Systems Section (GLASS).
Previously, he was a Postdoctoral Research Associate (January 2014 – August 2018) with the CArD Group at the Institute for Computing Systems Architecture (ICSA) in the School of Informatics at The University of Edinburgh, where he led the systems research of the H2020 BONSEYES project and the EPSRC AnyScale Applications project. He joined the ARCO Research Group in the Department of Computer Achitecture at Universitat Politecnica de Catalunya – BarcelonaTech in March 2012, where he was a Postdoctoral Researcher until Dec 2013. He received the Engineering and Ph.D. degrees in Computer Science from Universitat Politecnica de Valencia in Sept 2004 and Feb 2012, respectively. He was a member with the Networking Research Group (Sept 2005 – Feb 2012) and also with the Parallel Architectures Group (Dec 2009 – Feb 2012) in the Department of Computing Engineering at Universitat Politecnica de Valencia.

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Executing resource intensive Deep Neural Networks (DNN) on resource constrained devices at the edge provides many benefits, including reduction of latency by processing data locally without the overhead of Cloud communications. This is critical for real-time applications such as autonomous vehicles or critical IoT systems. Additionally, execution of DNN at the edge enhances privacy by processing private data locally; reduces bandwidth usage by minimizing data transfers; increases autonomy and resilience as edge devices continue to operate when disconnected from the network; and by optimizing DNN for the edge, allows DNN to operate within reduced power constraints while maintaining performance. Achieving these benefits within the constrained edge resources requires model compression and optimization, latency and real-time processing, hardware-software co-design, scalability and flexibility, and development and deployment complexity. To process complex DNNs at the edge, FPGA-based hardware acceleration is a promising approach. FPGAs can be customized for specific architectures, deliver high performance, operate more efficiently than GPUs, and be reconfigured for different DNNs, offering valuable flexibility. Our solution combines edge orchestration with DNN design frameworks that speed up design, optimize models for device size and energy, and convert them into FPGA implementations for hardware acceleration at the edge.

Author(s)/Presenter(s): Rashed Al Koutayni, German Research Center for Artificial Intelligence, Germany.
Alain Pagani, German Research Center for Artificial Intelligence, Germany.
Gerard Florence, CETIC, Belgium.
Lotfi Guedria, CETIC, Belgium.

The presenter Dr. Alain Pagani is Principal Researcher and deputy director of the Augmented Vision research department at the German Research Center for Artificial Intelligence (DFKI). His research interests include Artificial Intelligence, Computer Vision, Image Understanding, and Extended Reality. He is the coordinator of the Network of Excellence dAIEDGE about distributed AI at the edge, and the coordinator of the Horizon Europe project CORTEX² about remote cooperation using extended reality. He is lecturer at the University of Kaiserslautern-Landau, and he published over 100 articles in conferences and journals. His research finds applications in eXtended Reality for telecooperation (project “CORTEX²”, EU Grant 101070192), Artificial Intelligence and Computer Vision for Human-Robot cooperation (project “FLUENTLY”, EU Grant 101058680), Artificial Intelligence and Augmented Reality for analysis of extremely large data (project “ExtremeXP”, EU Grant 101093164).

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Face recognition systems, increasingly deployed on edge devices and servers, store high-dimensional embeddings from models like ArcFace for identity verification and search. While prior work shows such embeddings can reveal sensitive attributes, most target a single attribute at the per-user level in same-model settings. We present a unified study of both per-user and population-level demographic leakage, quantifying whether an adversary can predict attributes for individuals and recover aggregate demographic distributions of entire databases. We also introduce cross-model transfer evaluation, where probes trained on one model’s embeddings are applied to another’s, reflecting realistic adversaries without target-model access. Using FairFace and a pretrained ArcFace extractor, we measure leakage of gender, age range, and race, with per-user AUCs over 90% for gender and age range, and over 60% for race (obtained with basic MLP classifiers, making these estimates conservative); population-level estimates recover demographic proportions with low error. We further assess common blurring defenses, highlighting recognition–privacy trade-offs. Results indicate demographic leakage is structural, persisting from individual users to whole databases, and across different models, underscoring the need for stronger privacy safeguards in deployed face recognition systems, particularly in edge AI environments.

Author(s)/Presenter(s): Erica Liu, Eindhoven University of Technology, Netherlands.
Enrique Orozco Olivares, Eindhoven University of Technology, Netherlands.
Gijs Dubbelman, Eindhoven University of Technology, Netherlands.
Jean-Paul Linnartz, Eindhoven University of Technology, Netherlands.

The presenter Erica Liu is a PhD candidate at Eindhoven University of Technology researching privacy-preserving biometric identification for edge AI systems, focusing on privacy leakage in face recognition embeddings and with experience in hardware-aware quantization.

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This contribution is part of an overarching European project that aims to strengthen digital sovereignty in sustainable production in Europe by implementing AI tools and methods. In this context, Facility Management (FM) is of the highest importance for semiconductor industrial sites, as the entire production depends on the provision of the required secondary resources such as electricity, water or cooling at the right time, quality, and quantity.
In the project the partners Infineon Villach together with the Virtual Vehicle Research Center strive to develop approaches for an optimized FM with the help of AI. The innovative part is the development of AI-based approaches for monitoring the behaviour of cooling machines and their parameters. With the help of algorithms, AI tools and methods, we enable the detection and prediction of anomalies in the building cooling system.
Using an interactive web dashboard, users can filter tags, set parameters, calculate the number of anomalies detected, and visualize them clearly. While the initial focus of research was on detecting anomalies in time series data, the focus has increasingly shifted to predicting such anomalies. Machine learning models are trained to predict the probability of an anomaly before it occurs, enabling proactive measures to be taken.

Author(s)/Presenter(s): Michael Schmeja, Virtual Vehicle Research GmbH, Austria.
Silke Braun, Infineon Technologies Austria AG, Austria.

The presenter Dr. Michael Schmeja (59) has been working at the Virtual Vehicle Research Center in Graz since 2009 and is currently key researcher in the department NVH & Information Systems. From 1997 – 2009 he held various management positions at Siemens Mobility, where he was awarded Inventor of the Year in 2003. After studying mathematics, Mr. Schmeja earned his doctorate at the Institute of Railway Engineering at the Graz University of Technology.

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Regulation (EU) 2024/1689 (‘Artificial Intelligence Act’) establishes seven essential requirements addressing the risks to health, safety, and fundamental rights posed by certain AI systems (i.e., ‘high-risk AI systems’). In this context, edge AI providers may be required to adopt measures for bias detection and mitigation as well as human oversight, which will be instrumental in addressing risks of discrimination stemming from the development of their AI system(s). These requirements were, however, formulated in a general manner and will need to be operationalized further. This will require edge AI providers to reconcile the AI Act’s demands and the specificities of edge AI systems, in particular their decentralized architecture and close proximity to users. This presentation will examine the scope and function of these requirements with the aim to spark a discussion on the measures and safeguards needed to detect biases and ensure human oversight at the edge.

Author(s)/Presenter(s): Lydia Belkadi, KU Leuven, Belgium.
Jan De Bruyne, KU Leuven, Belgium.

The presenter Lydia Belkadi is a doctoral researcher at the Centre for IT & IP Law (CiTiP) of KU Leuven. Her research focuses on privacy and data protection aspects of AI technologies, with a particular focus on biometrics. Lydia was involved in the Innovative Training Network in Secure and PrivAcy preserving biometrics (TReSPasS-ITN) as a Marie Skłodowska-Curie doctoral candidate. Since 2023, she conducts research on Edge AI for the EU-funded Network of Excellence (NoE) for distributed, trustworthy, efficient and scalable AI at the Edge (dAIEDGE).

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This work presents the ongoing development of a handgun detection system for a smart city. This detector is expected to continuously analyse images taken by a surveillance camera installed at the entrance hall of a public building. The detector is deployed on an Jetson Orin Nano-based device with constrained computational resources. The development process began with an analysis of hardware limitations, which guided the design of lightweight yet effective deep learning models. Several processing pipelines were considered: a two-stage approach involving person detection followed by hand-region classification, and a direct handgun detection approach. Custom datasets were built and used to train models adapted to the device, while carefully avoiding overfitting. Performance was systematically evaluated using metrics such as mean Average Precision (mAP) and frames per second (FPS). The best trade-off between accuracy and inference speed was obtained with a YOLOv8s model trained exclusively for handgun detection, achieving 75.15% AP50 on the test set and sustaining 20 FPS. The detector was further integrated with MQTT for seamless communication with ThingsBoard, enabling the automatic transmission of detection events. Additional optimizations included fully headless execution and real-time parameter adjustment through terminal commands. Current work focuses on refining detection performance and exploring alternative models to further improve efficiency and accuracy.

Author(s)/Presenter(s): Juan Daniel Muñoz Navarrete, University of Castilla-La Mancha, Spain.
Hugo Albandea Merino, University of Castilla-La Mancha, Spain.
Oscar Deniz Suarez, University of Castilla-La Mancha, Spain.
Micaela Verucchi, Hipert srl, Italy.

The presenter Juan Daniel Muñoz Navarrete holds a degree in Electronic Engineering at the University of Castilla-La Mancha (UCLM) and is pursuing a Master’s in Systems and Control Engineering at the National University of Distance Education (UNED). As a member of VISILAB, his research focuses on computer vision and object detection, particularly in security-related applications.

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AI pushes ever closer to the network edge, slowly migrating from the heart of the network to the sensing devices themselves. One of the key goals of the EdgeAI community is to push AI capabilities ever closer to the micro-edge without loosing the functionalities that the deep- and meta-edge previously delivered. New edge platform developments facilitate this migration; unlocking new applications and making existing ones increasingly cost effective and performant. In this presentation we demonstrate the migration of a production level traffic management and analysis Nvidia based AI device to NXP and ST micro-edge hardware. This migration reduces power consumption, price tag and physical footprint, unlocking new opportunities without sacrificing functionality; While currently at prototype stage, a cheaper, lower power, solution could be deployed on a wider scale. For this specific application such migration facilitates the expansion of privacy preserving, city wide, traffic flow monitoring from single intersections to city wide deployment, for example. In short, moving towards the micro-edge lowers costs, enables large scale deployments and opens up new possibilities. Given these advantages migrating to the new generation of micro-edge platforms is not just viable, but compelling.

Author(s)/Presenter(s): Arno van der Weijden, Technolution B.V., Netherlands.
Luuk van der Weide, Technolution B.V., Netherlands.

The presenter Dr. Arno van der Weijden is a researcher at Technolution. Among other things he works on real world computer vision applications for industry. Examples include a highly accurate stereo vision application for binpicking of tomatoes, real time noise suppression in high throughput data acquisition (TB+/hour), digital draught measurements of ships in the harbour of Amsterdam, designing a computer vision system for powerline health checking in the railway industry and visualisation of gunshot residue for crime scene reconstruction. Arno also works on the electric grid congestion issue and bringing other systems to a production level.

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Digital Twin (DT) technology is becoming an essential tool for improving safety, availability, and maintenance in critical infrastructure. In hydrogen refuelling stations (HRS), detecting anomalies quickly is vital to prevent failures, avoid costly downtime, and maintain operational reliability. In this work, we propose an Edge-AI ready lightweight Digital Twin framework for anomaly detection, built using historical operational data from a real HRS — a dataset with 110 features and around 3 million complete records. Our methodology takes a step-by-step approach. We start with unsupervised learning methods—including statistics-based techniques like clustering and PCA, prediction-based methods like linear prediction and MLP, and reconstruction-based approaches like autoencoders and AE+CNN—to detect anomalies without labelled data. In the second step, we validate and refine these findings using supervised learning, applying both classical machine learning and deep learning classifiers. We then optimize the best-performing models for edge deployment using multi-phase quantization, structured pruning, and resource-aware execution strategies. Since we do not have a physical edge device, we create an edge simulation environment to mimic real-time data streaming and evaluate accuracy, latency, and model size. While our first deployment target is edge devices, future versions may run in the cloud for greater scalability. Our results show that starting with simple methods and progressively applying optimizations can significantly enhance HRS safety and reliability, while keeping the solution practical for resource-constrained hardware.

Author(s)/Presenter(s): Esin Öztürk, Framatome GmbH, Germany.
Francis Fomi Wamba, Framatome GmbH, Germany.

The presenter Esin Öztürk holds a physics degree from Istanbul Technical University and a master’s in Energy and Power Engineering from Tsinghua University. She is a PhD candidate at Framatome GmbH, specializing in developing digital twins for predictive maintenance in critical infrastructures and transforming these solutions into market-ready products. She is currently contributing to the Horizon Europe PANDORA project, focusing on innovative strategies to enhance reliability, efficiency, and resilience in industrial asset management.
Dr.-Ing. Francis Fomi Wamba is a senior expert and advisor with over 17 years’ experience in mechatronic systems, structural dynamics, and condition monitoring. He earned his engineering and PhD degrees at TU Darmstadt. At Areva (now Framatome), he developed the DIROM4i monitoring system and the patented AI-based CADIS analytics platform for industrial assets. As an academic and entrepreneur, he provides consulting, training, and data analytics strategy support to various industrial and academic clients.

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The presentation outlines the evolution of frameworks for end-to-end workflow automation, designed to address the complexities of building, deploying, and maintaining robust edge AI autonomous systems. It explores the integrated approach that automates the entire lifecycle, from data ingestion and model training to deployment on heterogeneous edge devices and continuous operational monitoring. The discussion highlights strategies for addressing the rise of agentic AI in workflow design and automation, particularly with the emergence of agentic edge AI systems that function with a degree of autonomy, understand intent, learn from context, and take initiative without relying on predefined instructions.

Author(s)/Presenter(s): Ovidiu Vermesan, SINTEF AS, Norway.

The presenter Ovidiu Vermesan is Chef Scientist at SINTEF Digital, Oslo, where he is involved in applied research on future edge autonomous intelligent systems and edge AI, wireless sensing devices and networks, smart systems integration, microelectronics design of integrated systems (analogue and mixed signal), IIoT. He holds a PhD in Microelectronics and a Master of International Business (MIB). His applied research activities focus on advancing edge AI processing, embedded electronics, wireless and smart sensing technologies, and the convergence of these technologies and applying the developments to applications such as green mobility, energy, buildings, autonomous systems, electric connected, autonomous, and shared vehicles, and industrial manufacturing. He is currently the coordinator of the Edge AI Technologies for Optimised Performance Embedded Processing (EdgeAI) project.

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The deployment of deep neural networks on edge devices requires a carefully constructed pipeline flow from algorithm design to hardware execution. In this work, we present a complete application development pipeline targeting J3DAI, a low-power DNN accelerator integrated in a 3D-stacked CMOS image sensor. Starting from model training in PyTorch, we use the Aidge framework for post-training quantization and hardware-specific transformations, enabling the direct generation of binary files optimized for J3DAI execution. We highlight practical considerations in network design, including quantization trade-offs, tiling strategies, and the mapping of common operators to accelerator primitives. Beyond the current deployment flow, we discuss new perspectives for extending accelerator support, such as advanced operator sets, adaptive memory partitioning, and tighter hardware-software co-design. Together, these contributions demonstrate a robust pipeline that bridges machine learning development with silicon-level efficiency, offering a practical route to real-time vision tasks directly on sensor.

Author(s)/Presenter(s): Michal Szczepanski, CEA-List, France.
Benoit Tain, CEA-List, France.
Raphael Millet, CEA-List, France.
Axel Farrugia, CEA-List, France.
Cyril Moineau, CEA-List, France.
Sebastien Thuries, CEA-List, France.

The presenter Michal Szczepanski is a research engineer at CEA List, where he has been working since 2015, progressing from an internship through doctoral research to a permanent position. He received the Ph.D. degree in Computer Science from Universite´ Blaise Pascal, Clermont-Ferrand, France, in 2018. His research interests include optimizing deep learning models for embedded execution through compression techniques targeting dedicated AI accelerators, and managing system-level challenges like multi-sensor data synchronization and calibration, with emphasis on real-time processing under resource constraints. He developed online stereo camera calibration technique for embedded processors, with applications in wearable smart glasses.

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Edge AI enables efficient, low-latency inference on distributed nodes, but fine-tuning models on these devices remains constrained by limited memory resources. While traditional approaches rely on cloud-based retraining, this practice raises privacy concerns and incurs high infrastructure costs. Advances in edge hardware, such as Nvidia’s Jetson platforms, now make on-device fine-tuning feasible; however, their shared memory architectures intensify the challenge of managing training-related memory overheads. Our profiling of PyTorch-based training workloads reveals that optimizer states alone can occupy up to 40% of total memory usage, persisting throughout training and surpassing the footprint of activations and gradients. To address this bottleneck, we present \name, a PyTorch-based module that enables memory-efficient fine-tuning on edge devices by offloading optimizer states to fast storage. Unlike compression or pruning methods, \name~preserves all optimizer information and selectively retrieves only the necessary state during backpropagation using a hook-based mechanism. It further minimizes I/O overhead through direct data movement strategies, sequential access patterns, and lightweight handling of momentum arrays. Our evaluation on the Nvidia Jetson Orin Nano demonstrates up to 69% memory reduction, enabling the training of models that baseline implementations cannot accommodate.

Author(s)/Presenter(s): Christos Kozanitis, FORTH, Greece.
Konstantina Orfanou, FORTH, Greece.

The presenter Christos Kozanitis is a research collaborator at FORTH-ICS. He received his M.S. and Ph.D in Computer Science and Engineering from the University of California, San Diego in 2009 and 2013 respectively. Parts of his phd work influenced products from companies such as Cisco and Illumina. He also held a two-year postdoctoral appointment at the AMP Lab of the University of California, Berkeley, where he used and adapted state of the art big data technologies to process large amounts of DNA sequencing data. His current work focuses on Deep Learning from both systems and modeling perspectives, supported by European and National funding. His research interests include edge AI challenges and serves as the hardware task leader for the dAIEDGE network of excellence.

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Graph Neural Networks (GNNs) have proven effective for intrusion detection by modelling the relational structure of network traffic. Yet, in practice, the cost of graph construction often dominates the overall inference time, limiting real-time deployment. In this work, we propose a GPU-accelerated framework that speeds up not only GNN inference but also the graph construction phase. Unlike traditional approaches that build the adjacency matrix from scratch for each input graph, our method introduces a precomputed default adjacency matrix generated in parallel on the GPU, which is then selectively modified for each graph instance. Node features are also computed in parallel using GPU threads, enabling end-to-end graph generation and inference entirely within GPU memory. Experiments on the 5G-NIDD dataset show a speedup of approximately 1.22× over CPU execution, while preserving detection accuracy. These results highlight the feasibility of deploying GNN-based intrusion detection systems in time-sensitive environments through co-optimization of algorithmic design and hardware execution.

Author(s)/Presenter(s): Ahmed Salah Tawfik Ibrahim, CNIT, Italy.
Emilio Paolini, Scuola Superiore Sant’Anna, Italy.
Filippo Cugini, CNIT, Italy.
Francesco Paolucci, CNIT, Italy.

The presenter Ahmed Ibrahim is a junior artificial intelligence researcher at Italy’s National Inter-University Consortium for Telecommunications (CNIT) where his work lies in the intersection between artificial intelligence and computer networks. This includes, but is not limited to, cybersecurity, federated learning and collaborative smart systems. He obtained his master’s degree in artificial intelligence and data engineering from the university of Pisa in 2023. Before joining CNIT, he was a research fellow at the Italian National Research Council (CNR) where his research focused on developing conversational agents for scientists. His areas of interest include computer vision, generative AI, federated learning, optimization and autonomous systems.

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Many applications in industry, agriculture and transportation domains benefit from AI inference at the edge.
The observed trend in image/video analysis is to increase the resolution of sensors, thus increasing the need for powerful, yet ultra low-power and low-latency hardware solutions.
In this presentation, we describe our recent new class of ASIC accelerators developed to meet these conflicting requirements: the Feature Extractor Accelerator (FEA). This solution enables processing up to HD images (1280×720) at 30 frames per second, using a fraction of the energy of the actual image sensor. Our approach combines two key principles: a feature extraction backbone with hard-wired weights and quantization plus transfer learning technique.
More in particular it consumes at most 23.2mW, with a 6.9ms latency, while reaching 70.42% accuracy on ImageNet. Iits power dissipation beats the best State-of-the-Art accelerators by 9× to 1000×.
Built in 22FDX, it addresses Classification, Semantic Segmentation and Multi-Object Detection applications by attaching a custom head.

Author(s)/Presenter(s): Mehdi Darouich, CEA-List, France.
Ivan Miro Panades, CEA-List, France.
Clement Turk, CEA-List, France.
Andrea Bocco, CEA-List, France.
Yann Picod, CEA-List, France.
Romain Lamaire, CEA-List, France.
Fabian Chersi, CEA-List, France.

The presenter Ivan Miro Panades received the M.S. degree in telecommunication engineering from the Technical University of Catalonia (UPC), Barcelona, Spain, in 2002, and the M.S. and Ph.D. degrees in computer science from Pierre and Marie Curie University (UPMC), Paris, France, in 2004 and 2008, respectively. He worked at Philips Research, Sureness, France and STMicroelectronics, Crolles, France, before joining CEA, Grenoble, France, in 2008, where he is currently a senior expert research engineer in digital integrated circuits. His main research interests are artificial intelligence, the Internet of Things, low-power architectures, energy-efficient systems, and Fmax/Vmin tracking methodologies.

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The integration of AI/ML into computing solutions continues to advance rapidly, but the growing performance and efficiency demands make reliance on cloud offloading impractical for critical domains such as healthcare, automotive, and industrial automation. To address this, the REBECCA project is developing a reconfigurable, heterogeneous, and power-efficient System-on-Chip (SoC) platform tailored for safe and secure edge AI. This work continues last year’s presentation by reporting progress toward the ongoing first silicon implementation of the REBECCA architecture in GlobalFoundries’ 22 nm (GF22) technology. The platform is built around a CVA6 RISC-V multi-core processor subsystem (RV64GC ISA, Linux-capable) tightly coupled with CNN, ML, IDS, and neuromorphic accelerators through a scalable chiplet-based interconnect. Dual-channel HyperRAM (512 MB) and SD-based storage provide a high- bandwidth shared memory model, while a large L2 cache and direct accelerator-to-memory access minimize data movement. Synthesizable RTL has been developed and optimized for GF22, with area estimations confirming the feasibility of integrating compute, memory, and accelerators within a low-power envelope. Alongside hardware, REBECCA delivers a complete software stack including OS, hypervisors, runtimes, and tool-suites. Validation across UAV-based PV inspection, AI-enabled appliances, semiconductor monitoring, and water infrastructure demonstrates REBECCA’s potential as a scalable foundation for next-generation edge AI.

Author(s)/Presenter(s): Iakovos Mavroidis, Technical University of Crete, Greece.
Konstantinos Georgopoulos, Exascale Performance Systems plc, Greece.
Andreas Brokalakis, Exascale Performance Systems plc, Greece.
Pavlos Malakonakis, Exascale Performance Systems plc, Greece.
Konstantinos Harteros, Exascale Performance Systems plc, Greece.
Dimitris Andronikou, Exascale Performance Systems plc, Greece.
Yannis Galanomatis, Exascale Performance Systems plc, Greece.
Charalampos Savvakos, Exascale Performance Systems plc, Greece.
Grigoris Chrysos, Technical University of Crete, Greece.
Ioannis Papaefstathiou, Exascale Performance Systems plc, Greece.

The presenter Dr. Iakovos Mavroidis is a member at the Technical University of Crete and co-founder/CTO of Exascale Performance Systems (EXAPSYS) plc. From 1991 to 1995, he was awarded two gold and two bronze medals in national competitions and two honorable mentions in International Olympiads in Mathematics and Computer Science. He received his B.Sc. in Computer Science from the University of Crete in 1999 (GPA 9.29/10) and his M.Sc. from UC Berkeley in 2001 (GPA 3.93/4). He has worked at Sun Microsystems, MIPS Technologies—where he led the R20K microprocessor design—Ellemedia Technologies, Virtual Trip, and Kaleao Ltd. From 2004 to 2006, he was also a Visiting Professor at the University of Crete. He received his Ph.D. from the Technical University of Crete in 2011. He has coordinated several EU projects, including RAPID H2020 and OPTIMA EuroHPC, and is currently leading the REBECCA KDT JU project.

The presenter Dr. Georgopoulos is an affiliated researcher at the Microprocessor and Hardware Lab at the Technical University of Crete and at the Institute of Communication and Computer Systems (ICCS) at the National Technical University of Athens. He received his degree and PhD in Electronic Engineering in 2001 and 2007, respectively, from the Department of Engineering at Lancaster University in the UK. Dr. Georgopoulos has taught and conducted research at both national and European levels, in collaboration with Lancaster University, the Athens University of Economics and Business (AUEB), the Technical University of Crete, and the Foundation for Research and Technology – Hellas (FORTH) for the past 15 years. His primary responsibility has been the technical implementation of complex subsystems based on reconfigurable logic. Some of the most important projects include AFORMI (#ESPA 207-1013), ECOSCALE (#671632), CYRENE (#952690), ENERMAN (#958478), and SECOPERA (#101070599). Currently, Dr. Georgopoulos holds the management responsibility for two European research projects, REBECCA (#101097224) and MEDIATE (#101168465), as Project Manager. Additionally, he is a member of the organizing committee of the Key Digital Technologies (KDT) EDGE AI Cluster, an EU initiative aimed at collaboration and coordination of all research achievements and activities in state-of-the-art technologies at the edge utilizing artificial intelligence techniques.

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Edge computing allows running applications without the added latency to transfer data to datacenters. With an application processing video stream, an AI agent can be run close to the end user using these decentralized servers. Remote Direct Memory Access (RDMA) is a fast network transport protocol (100Gbps and more) that can be run at the edge to communicate between the different systems. This allows processing the video stream in Data Processing Units (DPUs), instead of running in servers, where CPU usage is a scarce resource. To demonstrate this, we implement a demo application of a virtual try-on by levering RDMA and DPUs, allowing a better usage of hardware resources. We leverage GStreamer, an industry-standard framework used to process media streams and implement an RDMA network plugin for BlueField DPUs.

Author(s)/Presenter(s): Raphael Frantz, NVIDIA, Italy.
Romain Pouillard, Institute Pascal, France.

The presenter Raphael Frantz received his Master’s degree from the Université de Reims Champagne-Ardenne in France. He is currently pursuing a PhD at Eindhoven University of Technology in collaboration with NVIDIA, as part of the QUARC project, a European research initiative focused on the implementation and integration of post-quantum cryptography. His research focuses on the architecture and performance of Data Processing Units, a new class of SmartNICs that integrate hardware and software accelerators to optimize data center operations. His interests include Remote Direct Memory Access and the offloading of communication tasks to SmartNIC hardware to improve efficiency and scalability in distributed computing environments.

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AI is transforming the automotive industry with diverse use cases beyond vision and autonomous driving. Multiple applications benefit from AI to enhance performance at the edge. This presentation will cover some of these use cases, with a focus on hardware and ecosystem support to enable seamless implementation.

Author(s)/Presenter(s): Giuseppe Russo, STMicroelectronics, Italy.

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Spiking Neural Networks (SNNs) enable sparse and event-driven computations, especially promising for edge applications with limited energy budget. One recent line of research suggests the integration of the attention layer into spiking models as an opportunity to close the gap with non-spiking approaches, preserving the inherent efficiency of binary computation. This work investigates a compact hardware architecture tailored for spiking transformers deployment on resource-constrained FPGAs, suitable to fit the wearable domain, such as the Lattice iCE40UP5K. Compared to the alternatives in the literature, limited to high-end FPGA platforms, we focus on resource minimization, demonstrating suitability for real-time execution in biological signal processing.

Author(s)/Presenter(s): Gianluca Leone, University of Cagliari, Italy.
Paola Busia, University of Cagliari, Italy.
Mauro Orrù, University of Cagliari, Italy.
Paolo Meloni, University of Cagliari, Italy.

The presenter Paola Busia received the Ph.D. degree in electronics and computer engineering from the Università degli studi di Cagliari, Cagliari, Italy, in 2023. She is currently an Assistant Professor with the Università degli studi di Cagliari. Her main research interests include power efficient processing architectures for embedded applications and for at-the-edge AI.

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Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (CIM) accelerator optimized for Spiking Neural Networks (SNNs) Inference. Our proposed architecture employs a multiport SRAM design with multiple decoupled Read ports to enhance the throughput and Transposable ReadWrite ports to facilitate online learning. Furthermore, we develop an Arbiter circuit for efficient data-processing and port allocations during the computation. Results for a 128×128 array in 3nm FinFET technology demonstrate a 3.1× improvement in speed and a 2.2× enhancement in energy efficiency with our proposed multiport SRAM design compared to the traditional single-port design. At system-level, a throughput of 44 MInf/s at 607 pJ/Inf and 29mW is achieved.

Author(s)/Presenter(s): Rajendra Bishnoi, University of Delft, Netherlands.

The presenter Rajendra Bishnoi is currently an Assistant Professor with the Computer Engineering Group, Delft University of Technology (TU-Delft). He received the Ph.D. degree in computer science from the Karlsruhe Institute of Technology (KIT), Germany, in 2017. He was a Research Leader with the MRAM Group, for more than two years. From 2006 to 2012, he was a Design Engineer with Freescale (now NXP), where he was a part of the Technical Solution Group in memory and SoC flow. His current research interests include neuromorphic computing, computation-in-memory, and emerging technologies. He was a recipient of the EDAA Outstanding Dissertation Award in 2017. He has served on the TPC for several prominent conferences, including ICCAD’25, DAC’25, DATE’25, DATE’24, ICCAD’24, ETS’24, DATE’23, and DATE’22. Also, he has held the role of Topic Track Chair for DATE’26, DATE’25, DATE’24 and ETS’24. He was also a guest editor for the Frontiers in Neuroscience Journal in 2022.

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As edge AI applications demand increasingly sophisticated processing capabilities while operating under severe power constraints, traditional computing architectures face fundamental limitations. Neuromorphic sensing and computing, inspired by the human eye and brain, offers a paradigm shift toward ultra-low power intelligent edge devices. This presentation introduces Spiking Neural Networks (SNNs) as a cornerstone technology for next-generation edge AI systems, demonstrating how SynSense’s neuromorphic technologies address critical challenges in power efficiency and real-time processing.
We highlight the fundamental principles of SNNs and their event-driven computation model, resulting in dramatic power savings compared to conventional artificial neural networks. We also introduce SynSense’s neuromorphic hardware and software frameworks, showcasing practical implementations in computer vision and natural signal processing. Through real-world prototypes, we demonstrate how neuromorphic edge devices achieve millisecond-level inference latencies while consuming orders of magnitude less power than traditional processors.
The discussion concludes with insights into the broader potential of neuromorphic computing for next-generation edge AI applications.

Author(s)/Presenter(s): Arslan Ali, SynSense, Switzerland.
Mina Khoei, SynSense, Switzerland.

The presenter Arslan Ali is a Computer Vision Engineer at SynSense, a leading neuromorphic technology company based in Zurich, Switzerland. Specializing in event-driven computer vision applications, Arslan focuses on the integration of event cameras with Spiking Neural Networks (SNNs) for ultra-low power edge AI solutions. His expertise lies in developing and optimizing neuromorphic vision systems that leverage the natural synergy between event-based sensors and spike-based processing architectures. At SynSense, Arslan contributes to the practical deployment of neuromorphic processors and software frameworks for real-time vision applications in resource-constrained environments. His work bridges theoretical neuromorphic computing concepts with practical computer vision implementations, particularly in scenarios requiring continuous operation under strict power budgets.

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Demonstrator VCD1.3 of the EdgeAI project integrates a minimalistic sensing approach with a neuromorphic processor for real-time gesture recognition at the edge. Developed by ams OSRAM and SynSense, the system processes optical interferometric signals to classify three gestures—swipe left, swipe right, and tap—using Spiking Neural Networks (SNNs). It achieves 40 fps with ultra-low power consumption (50 µW) and a compact memory footprint (~100 KB). The sensor relies on self-mixing interferometry, where a near-infrared VCSEL (Vertical-Cavity Surface-Emitting Laser) reflects off a target (the touch interface) and re-enters the laser cavity, producing measurable interferometric disturbances. The hardware, established during the first two years of the project, is undergoing extensive validation in year three. We conduct cross-user generalization tests, noise robustness evaluations, and comparisons with conventional CNN models. Next steps include finalizing verification activities—such as model stability analysis and strategy development—and expanding CNN benchmarking through failure case analysis and performance metrics. These efforts aim to enhance system reliability and broaden applicability in real-world human–machine interfaces.

Author(s)/Presenter(s): Daniel Najer, ams International AG, Switzerland.
Florent Monay-Michaud, ams International AG, Switzerland.
Francesco Paolo D’Aleo, ams International AG, Switzerland.
Bastien Moysset, ams International AG, Switzerland.
Brett Anthoine, ams International AG, Switzerland.
Hugues Salamin, ams International AG, Switzerland.
Mina Khoei, SynSense AG, Switzerland.
Dylan Muir, SynSense AG, Switzerland.

The presenter Dr. Daniel Najer is Associate Project Manager for Public Funding at ams OSRAM, where he leads EU and nationally funded R&D initiatives in photonics, sensors, and intelligent systems. He holds a PhD in Experimental Physics from the University of Basel and contributed to a Nature-published advancement in quantum photonics, bringing deep technical expertise to his role. At ams OSRAM’s Innovation Office, he expanded his scope by driving initiatives in emerging technologies beyond the company’s core business—through technology scouting, innovation workshops, and project development. He spearheaded the creation of several high-impact demonstrators in consumer electronics, including AI/ML-driven Eye Tracking for AR/VR and diverse applications of Self-Mixing Interferometry. His work resulted in more than 20 scientific publications and patents filings, underscoring his impact across research and innovation.

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We propose a novel model optimization pipeline tailored for trustworthy edge AI, with a specific focus on automated inspection of electricity grid insulators. Our pipeline integrates hardware-aware model search, hyperparameter tuning, and flat minima training strategies to construct optimized deep learning models that maintain high prediction reliability on resource-constrained edge devices. Unlike traditional approaches, we introduce the Area Under the Generalized Risk Coverage Curve (AUGRC) as a core metric for model selection, enabling enhanced failure prediction and reducing the risk of silent misclassifications. The pipeline supports selective offloading based on calibrated confidence scores, enabling dynamic collaboration between on-drone lightweight models and high-accuracy edge servers within a Hierarchical Inference (HI) framework. This approach ensures that real-time constraints are met while maximizing accuracy and efficiency in cost and energy. Flat minima training techniques, such as SAM and SWA, are leveraged to preserve confidence separability between correct and incorrect predictions, boosting model trustworthiness even under hardware constraints. For the validation, we employ: (i) the faulty insulators annotated open-source IDID dataset, (ii) different hardware platforms for the on-drone equipment, such as Raspberry Pi 5 equipped with either HAILO-8L or Orca M.2 (DRAM) or Google Coral AI accelerators, STM32MP257F-EV1, and STM32N6570-DK platforms, and different platforms acting as edge servers, such as NVIDIA Jetson Orin Nano. Αblation and sensitivity studies are conducted to validate the benefits of our approach.

Author(s)/Presenter(s): Alexandros Maxairas, AI laboratory of enakronIC PC, Greece.
Nikolaos Tzanis, AI laboratory of enakronIC PC, Greece.
Athanasios Bachoumis, AI laboratory of enakronIC PC, Greece.

The presenter Alexandros Machairas is a Junior Edge AI Engineer at EnakronIC PC. He holds an integrated MSc degree in Electrical and Computer Engineering from the University of Patras, Greece, in 2024, with research focused on predictive maintenance and trustworthy AI. In the past, he has worked in the laboratory of applied microelectronics at the University of Patras as a researcher. His expertise spans end-to-end design of edge AI pipelines, with hands-on experience deploying optimized deep learning models on resource-constrained hardware such as STM32, HAILO, and Google Coral platforms. His current work centers on hardware-aware model optimization for reliable, real-time inspection of electricity infrastructure.

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We present DNSGuard, an edge-native DNS firewall that uses a locally hosted large language model (LLM) to intelligently analyze domain queries in real time. Designed for scenarios where privacy, low latency, and autonomy are essential, DNSGuard detects threats directly at the network edge without depending on cloud APIs or external telemetry.
An on-device LLM (e.g., LLaMA via GPT4All) reasons about the intent, structure, and semantics of queried domains, enabling detection of suspicious or malicious sites even without pre-existing blacklists. It can identify phishing, impersonation, and other threats through pattern recognition, and in uncertain cases, it performs secondary checks such as SSL certificate analysis or similarity matching against trusted domains.
Optimized for focused DNS inspection, DNSGuard achieves strong detection performance using lightweight models, allowing smooth operation on modest edge hardware. A simple web dashboard provides live statistics, filtering controls, and monitoring options.
As a proof-of-concept, DNSGuard demonstrates that advanced AI models can run effectively on resource-constrained devices for real-time cybersecurity. By moving semantic inspection to the edge, it strengthens network defences, preserves privacy, and illustrates a novel application of generative LLMs in edge security. Performance tests have been carried out in GPUs (ie Jetson) and CPUs.

Author(s)/Presenter(s): Athanassios Boufis, University of Patras, Greece.
Kyriakos Vlachos, University of Patras, Greece and National Inter-University Consortium for Telecommunications (CNIT), Italy.
Filippo Cugini, National Inter-University Consortium for Telecommunications (CNIT), Italy.

The presenter Kyriakos Vlachos received his Dipl.-Ing. degree in electrical and computer engineering from the National University of Athens (NTUA), Greece, in 1998 and his Ph.D. in electrical and computer engineering, also from NTUA, in 2001. From 1997 to 2001 he was a Senior Research Associate in the Photonics Communications Research Laboratory (ICCS/NTUA). In April 2001 he joined Bell Laboratories, Lucent Technologies, working on behalf of the Applied Photonics Group. During 2003, he was also a member of the Computer Engineering Laboratory of the Technical University of Delft, and since 2005 he has been a Faculty Member of the Computer Engineering and Informatics Department of the University of Patras, Greece. His research interests include high-speed networks, edge security, network security and open source SW and HW tools.

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The poster presents a collection of real-world applications demonstrating the transformative impact of edge AI in digital industry. By bringing computational intelligence closer to the source of data, these projects showcase significant advancements in efficiency, real-time processing, and quality control across various industrial sectors. The demonstrators highlight the versatility and power of edge AI to create more intelligent, responsive, and efficient industrial processes, paving the way for the next generation of smart manufacturing.

Author(s)/Presenter(s): Silke Braun, Infineon Technologies Austria AG, Austria.

The presenter Silke Braun completed her studies in microsystems engineering at Mittweida University of Applied Sciences (Germany). In 2017, she started working at Infineon Technologies Dresden as a defect density and metrology engineer; since 2018 in Villach (Austria). She strengthened her knowledge in the field of quality management. Since 2022, she focuses her work on the field of funding and works in various EU-funded projects.

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The poster showcases an edge AI-driven system designed to improve yield prediction in vineyards, ultimately enhancing both agricultural productivity and sustainability. By deploying advanced computing at the edge, the system delivers precise, real-time yield estimations. This facilitates more efficient resource management, reduces waste, and promotes sustainable farming practices through optimized, data-driven decision-making in vineyard operations.

Author(s)/Presenter(s): Marcello Coppola, STMicroelectronics, France.

The presenter Marcello Coppola is a Technical Director at STMicroelectronics, in charge of the implementation of several research projects, including overseeing day-to-day field-based activities related to System-on-Chip for Consumer, Space, Automotive, IoT, Healthcare, with particular emphasis in Network-on-Chip, heterogeneous multi-core hardware and software architectures which include CPU, GPU and accelerators. He’s co-author and/or co-editor of different books, 24 patents and more than 100 papers/presentations in international conferences. He is serving as program and organizing member in numerous top international conferences and workshops currently drives the concrete realization of the advanced R&D for the communication architecture, verification and modelling inside STMicroelectronics.

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The poster explores how edge AI delivers high-quality situational awareness and triggers autonomous responses in digital society environments. Focusing on industrial machine rooms, energy substations, home/office settings, and robotized manufacturing, it highlights value chain demonstrators that showcase embedded intelligence for real-time decision-making. This work enhances safety, efficiency, and autonomy across critical infrastructure and everyday spaces, demonstrating the impact of edge AI on modern digital life.

Author(s)/Presenter(s): Fetze Pijlman, Signify, Netherlands.

The presenter Fetze Pijlman is a Principal Scientist at Connected Systems Signify Research, an AI, machine learning, and signal processing expert with over 15 years of experience in R&D environments. Driven by a passion for solving complex technical problems and making a significant organizational impact, Fetze excels in leading small teams with an agile and pragmatic approach. His expertise spans algorithm development, programming, statistics, theoretical physics, and optics. He has a strong track record in developing intelligent lighting control systems, including reinforcement learning on edge devices, time series analysis, and leveraging generative AI for customer interactions. Fetze is also deeply involved in academic collaborations, guiding PhD students, and contributing to several EU and Dutch research projects focused on Edge AI and foundation models for industry.

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Abstract:
Deep neural networks (DNNs) are increasingly deployed on embedded accelerators for real-time applications but face constraints such as limited area, power, and latency. Network-on-Chip (NoC)-based dataflow architectures help address these challenges by flexibly distributing computations and data across processing elements, adapting to different DNN layers while optimizing efficiency. However, mapping DNN operations on NoCs is complex due to their multi-dimensional nature and the large design space, requiring systematic tools for exploration and optimization. To tackle this, we propose a framework for NoC-based dataflow architectures that estimates performance, power, and area (PPA). The framework combines a hardware model defining architectural granularity, PPA models assessing efficiency, and a mapping model analysing operation costs across layers. Preliminary results demonstrate a first functional version of the PPA models, supported by a rich and representative dataset, providing performance, power, and area estimates closely aligned with the actual behaviour of the accelerator.

Author(s)/Presenter(s): Hana Krichene, CEA, France.
William Fabre, CEA, France.
Caaliph Andriamisaina, CEA, France.
Rohit Prasad, CEA, France.

The presenter Hana Krichene is a researcher at CEA, specializing in low-power AI hardware architectures for embedded and edge systems. She earned her PhD in 2015 and focuses on designing energy-efficient AI solutions for resource-constrained environments. Hana has contributed to several European research projects, most recently Neurokit2E, participating in the development of a performance and power estimation tool for dataflow architectures based on Network-on-Chip designs. Her expertise spans hardware modeling, energy-aware design, and optimization, enabling efficient deployment of AI on embedded platforms.

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